entrega 3 :ejemplos VHDL

sábado, 29 de mayo de 2010

entrega 3 :ejemplos VHDL


Ejemplo 12:
Diseñar en VHDL, un transcodificador,del codigo 84-2-1 al jhonson de 5bits
-------------------------------------------------
-- electronico-etn.blogspot.com
-- ejemplos practiicos
-- transcodificador de del codigo 84-2-1 al

-- jhonson de 5 bits
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity transcodificador is
port
    (cod: in std_logic_vector (3 downto 0);
    Jhonson5bits: out std_logic_vector (4 downto 0));
end transcodificador;

architecture rtl of transcodificador is
begin
    PROCESS(cod)
    BEGIN
        CASE cod IS
        WHEN "0000" => Jhonson5bits <= "00000";
        WHEN "0111" => Jhonson5bits <= "00001";
        WHEN "0110" => Jhonson5bits <= "00011";
        WHEN "0101" => Jhonson5bits <= "00111";
        WHEN "0100" => Jhonson5bits <= "01111";
        WHEN "1011" => Jhonson5bits <= "11111";
        WHEN "1010" => Jhonson5bits <= "11110";
        WHEN "1001" => Jhonson5bits <= "11100";
        WHEN "1000" => Jhonson5bits <= "11000";
        WHEN "1111" => Jhonson5bits <= "10000";
        WHEN OTHERS => Jhonson5bits <= "00000";
        END CASE;

    END PROCESS;
END rtl;

Ejemplo 13:
Diseñar en VHDL, generador de bits para la coreccion de errores de un Bcd aiken
Solucion:
--------------------------------------------------
-- electronico-etn.blogspot.com
-- ejemplos practiicos
-- deteccion y correccion de errores
--------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity DyCdeError is
port
    (I: in std_logic_vector (3 downto 0);
    bits: out std_logic_vector (7 downto 1));
end DyCdeError;

architecture rtl of DyCdeError is
begin
    PROCESS(I)
    BEGIN
        CASE I IS
        WHEN "0000" => bits <= "0000000";
        WHEN "0001" => bits <= "0000111";
        WHEN "0010" => bits <= "0011001";
        WHEN "0011" => bits <= "0011110";
        WHEN "0100" => bits <= "0101010";
        WHEN "1011" => bits <= "1010101";
        WHEN "1100" => bits <= "1100001";
        WHEN "1101" => bits <= "1100110";
        WHEN "1110" => bits <= "1111000";
        WHEN "1111" => bits <= "1111111";
        WHEN OTHERS => bits <= "0000000";
        END CASE;
    END PROCESS;
END rtl;

 Ejemplo 14:
Diseñar en VHDL, diseñe un sumador simple, sin acarreo
Solucion:
-------------------------------------------
-- electronico-etn.blogspot.com
-- APLICACION DE MULTIPLEXORES
-- suumador
-------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_arith.ALL ; --define 1:signed 2:unsigned 3:integer

ENTITY sumsen IS
    PORT
        (A,B: IN signed (4 downto 0) ;
        S: out signed (4 downto 0) );
END sumsen ;

ARCHITECTURE rtl OF sumsen IS
BEGIN
S    <=    A + B ;
END rtl ;

Ejemplo 15:
Diseñar en VHDL, diseñe un sumador simple, con acarreo
----------------------------------------
-- electronico-etn.blogspot.com
-- ejemplos practiicos
----------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_unsigned.ALL ;


ENTITY sumaca IS
    PORT
        (A,B: IN std_logic_vector (3 downto 0);
        ci: in std_logic;
        S: out std_logic_vector (3 downto 0);
        co: out std_logic);
END sumaca ;

ARCHITECTURE entera OF sumaca IS
signal suma: std_logic_vector(4 downto 0);
BEGIN
    suma <=    ('0'& A) + B + ci ;     S <= suma(3 downto 0);
    co <= suma(4);
END entera ;

Ejemplo 16:
Diseñar en VHDL, un sumdor de 8 bits con signo
Solucion:
---------------------------------
-- electronico-etn.blogspot.com
-- ejemplos practiicos
---------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_arith.ALL ;


ENTITY sumador8bits IS
    PORT
        (A,B: IN unsigned (7 downto 0) ;
        C: IN signed (7 downto 0) ;
        D: in std_logic_vector (7 downto 0) ;
        S: out unsigned (8 downto 0) ;
        T: out signed (8 downto 0) ;
        U: out signed (7 downto 0) ;
        v: out std_logic_vector (8 downto 0) );
END sumador8bits ;

ARCHITECTURE rtl OF sumador8bits IS
BEGIN
S    <=    ('0' & A) + ('0' & B) ;
T    <=    A + C ;
U    <=    C + SIGNED(D) ;
V    <=    C - UNSIGNED(D) ;
END rtl ;

muy pronto mas ejemplos.....

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